Semiconductor device and corresponding method

ABSTRACT

A semiconductor device comprises at least one semiconductor die electrically coupled to a set of electrically conductive leads, and package molding material molded over the at least one semiconductor die and the electrically conductive leads. At least a portion of the electrically conductive leads is exposed at a rear surface of the package molding material to provide electrically conductive pads. The electrically conductive pads comprise enlarged end portions extending at least partially over the package molding material and configured for coupling to a printed circuit board.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.17/120,996, filed Dec. 14, 2020, now U.S. Pat. No. 11,749,588, whichclaims the priority benefit of Italian Application for Patent No.102019000024259, filed on Dec. 17, 2019, the contents of which arehereby incorporated by reference in their entireties to the maximumextent allowable by law.

TECHNICAL FIELD

The description relates to manufacturing semiconductor devices.

One or more embodiments may be applied to manufacturing integratedcircuits (ICs).

BACKGROUND

Semiconductor devices such as integrated circuits may be provided withpackages of various types. For instance, quad-flat no-leads (QFN)packages and land grid array (LGA) packages are examples ofsurface-mount technology (SMT) packages known in the art.

QFN packages are near chip-scale plastic encapsulated packages providedwith a planar leadframe substrate, wherein perimeter lands on thepackage rear (e.g., bottom) side are configured to provide electricalconnections to a printed circuit board (PCB). The leads of the leadframeare thus fully incorporated in the package molding compound. QFNpackages may include an exposed thermal pad to improve heat transfer outof the integrated circuit, into the printed circuit board.

LGA packages also have leads fully incorporated in the package moldingcompound, and comprise a (rectangular) grid of contacts on the bottomside of the package. The contacts on the package are configured to becoupled to a grid of contacts on the PCB.

Both QFN and LGA packages (as well as other SMT packages) do not haveexternal leads, but rather have “lands” or “pads” that are directlycouplable to the PCB pads for soldering by means of solder paste orsolder alloy. The mounting (soldering) step may be complex and mayresult in a wide variability of welding strength and structure.Additionally, the different coefficients of thermal expansion betweenthe package and the printed circuit board may lead to high stress in thesolder material and/or to high thermal fatigue of QFN/LGA packages oncemounted on a printed circuit board.

In this context, the use of “wettable flanks” is known in the art.Wettable flanks help increase wettability of the leads with the purposeof improving solder adhesion and overall welding strength by increasingthe solder attachment area on the vertical side of the lands or pads.Wettable flanks may only slightly improve the solder joint reliability,and facilitate automatic optical inspection of the solder joint afterthe surface mounting process, for surface mount process control.

Packaged semiconductor devices providing improved solder jointreliability and/or stronger anchorage to the PCB are desirable.

There is a need in the art to contribute in providing packagedsemiconductor devices, e.g., comprising a QFN- or LGA-type package, withimproved solder joint reliability and/or stronger anchorage to theprinted circuit board.

SUMMARY

One or more embodiments may relate to a semiconductor device (e.g., anintegrated circuit).

One or more embodiments may relate to a corresponding method ofmanufacturing semiconductor devices.

One or more embodiments may provide a packaged semiconductor device(e.g., comprising a QFN or LGA package) comprising at least onesemiconductor die electrically coupled to a set of electricallyconductive leads, and package molding material molded over the at leastone semiconductor die and the electrically conductive leads. At least aportion of the electrically conductive leads may be exposed at a rearsurface of the package molding material to provide electricallyconductive pads. The electrically conductive pads may comprise enlargedend portions extending at least partially over the package moldingmaterial and configured for coupling to a printed circuit board.

BRIEF DESCRIPTION OF THE DRAWINGS

One or more embodiments will now be described, by way of example only,with reference to the annexed figures, wherein:

FIG. 1 is a perspective view exemplary of a semiconductor devicecomprising a QFN package, shown upside-down (i.e., with the rear sidefacing upwards);

FIG. 2 is a view of the rear side of the semiconductor device of FIG. 1;

FIG. 3A is a magnified view of a portion of the rear side of thesemiconductor device of FIG. 2 ;

FIG. 3B is a side view of the portion of the semiconductor device ofFIG. 3A mounted on a printed circuit board;

FIG. 4A is a magnified view of a portion of the rear side of asemiconductor device according to embodiments;

FIG. 4B is a side view of the portion of the semiconductor device ofFIG. 4A mounted on a printed circuit board; and

FIGS. 5A to 5G are exemplary of steps of a method of manufacturingsemiconductor devices according to embodiments.

DETAILED DESCRIPTION

In the ensuing description, one or more specific details areillustrated, aimed at providing an in-depth understanding of examples ofembodiments of this description. The embodiments may be obtained withoutone or more of the specific details, or with other methods, components,materials, etc. In other cases, known structures, materials, oroperations are not illustrated or described in detail so that certainaspects of embodiments will not be obscured.

Reference to “an embodiment” or “one embodiment” in the framework of thepresent description is intended to indicate that a particularconfiguration, structure, or characteristic described in relation to theembodiment is comprised in at least one embodiment. Hence, phrases suchas “in an embodiment” or “in one embodiment” that may be present in oneor more points of the present description do not necessarily refer toone and the same embodiment. Moreover, particular conformations,structures, or characteristics may be combined in any adequate way inone or more embodiments.

Throughout the figures annexed herein, like parts or elements areindicated with like references/numerals and a corresponding descriptionwill not be repeated for brevity.

The references used herein are provided merely for convenience and hencedo not define the extent of protection or the scope of the embodiments.

By way of introduction to the detailed description of exemplaryembodiments, reference may be first had to FIGS. 1 and 2 , which areexemplary of a semiconductor device 10 comprising a QFN package.

While reference is made mainly to QFN packages in the presentdescription and drawings for the sake of conciseness, one or moreembodiments may be applied to other types of “leadless” packages, e.g.,LGA packages.

As current in the art, together with other elements/features not visiblein the Figures, a semiconductor device 10 as exemplified herein maycomprise package molding material 100 encapsulating a semiconductor die(not visible in FIGS. 1 and 2 ), the molding material 100 being shapedto provide a rear (e.g., bottom) side 10A of the semiconductor device 10configured for electrical and mechanical coupling to a printed circuitboard.

A set of electrically conductive “lands” or “pads” 12 may be provided onthe rear (or bottom) side 10A, e.g., at the periphery thereof, asillustrated in FIGS. 1 and 2 . Additionally or alternatively, the pads12 may be arranged over the entire area of the rear side 10A, ascustomary in LGA packages. The pads 12 may be electrically coupled tothe semiconductor die encapsulated in the molding material 100.

Optionally, the package may include an exposed thermal pad 14 on therear side 10A. The thermal pad 14 may be thermally coupled to thesemiconductor die encapsulated in the molding material 100 to improveheat transfer out of the integrated circuit 10.

Overall, the electrical pads 12 and the thermal pad 14 may provide theleadframe of the integrated circuit 10.

The (minimum) spacing between two adjacent pads 12 may be constrained bymanufacturing constraints of the leadframe. Typically, the correspondingsolder pads on a PCB may be wider and/or less spaced. For instance, FIG.2 shows a bottom view of an exemplary integrated circuit 10 havingelectrical pads 12 and a thermal pad 14 (illustrated with solid lines),and a corresponding exemplary arrangement of solder pads 12′ and 14′ asmay be present on a printed circuit board configured for coupling to theintegrated circuit 10.

FIG. 3A is a magnified view exemplary of a portion of the rear side 10Aof the integrated circuit 10, e.g., portion 20 illustrated in FIG. 2 .FIG. 3B is a corresponding side view of portion 20, exemplary of theintegrated circuit 10 mounted on a printed circuit board by means ofsoldering material 32 interposed between the electrical pads 12 of theintegrated circuit 10 and the respective solder pads 12′ on the PCB 30.

It is noted that, as a consequence of the spacing D_(o) between pads 12being (considerably) larger than the spacing d between pads 12′,electro-mechanical coupling of the integrated circuit to the PCB 30 mayturn out to be unsatisfactory.

In one or more embodiments as exemplified in FIGS. 4A and 4B,reliability of such electro-mechanical coupling may be improved byincreasing the area of the electrical pads 12 of the integrated circuit10.

FIG. 4A is a magnified view exemplary of a portion 20 of the rear side10A of an integrated circuit 10 according to one or more embodiments.FIG. 4B is a corresponding side view of portion 20, exemplary of theintegrated circuit 10 mounted on a printed circuit board by means ofsoldering material 42.

As exemplified herein, a metallic layer may be selectively provided atthe pads 12 after molding of the package material 100 to provideenlarged end portions 44 of the pads. The enlarged end portions 44 maythus partially extend over the molding material 100 at the interfacebetween the pads 12 and the molding material 100 (e.g., “sidewise” ofthe body portion 12 of the pads which are embedded in the moldingmaterial), thereby increasing the area of the pads suitable forelectrical and/or mechanical coupling to the soldering pads 12′.

Therefore, in one or more embodiments, a (thick) “pedestal” of metalmaterial may be grown over the surface of the pads 12 and/or 14 leftexposed by the molding material 100, thereby providing larger pads(i.e., providing a reduced spacing D_(n) between pads 12, which increasethe soldering surface) and an increase of the standoff between thesemiconductor package 100 and the printed circuit board 30. As a result,solder joint reliability may be improved and/or a stronger anchorage ofthe integrated circuit to the PCB may be obtained.

In one or more embodiments, the enlarged end portions 44 may be provided(e.g., grown) over the pads 12 and/or 14 after molding of the packagematerial 100 by means of galvanic plating.

Providing the enlarged end portions 44 by galvanic plating may beadvantageous insofar as it may facilitate growing the metal 44(sidewise) over the molding compound 100 at the interface between thepads 12 and/or 14 and the molding compound 100, i.e., it may facilitateproperly increasing the area of the pads (as exemplified in FIG. 4B).

Additionally or alternatively, any other selective metal depositiontechnique that would result in an isotropic growth of metal at the pads12 and/or 14 may be used to form the enlarged portions 44.

In one or more embodiments, the thickness of the enlarged end portions44 may be in the range of 10 μm to 100 μm, preferably 50 μm to 70 μm.

In one or more embodiments, the enlarged end portions 44 may extend(sidewise) over the molding compound 100 from the interface between therespective body portion of pad 12 and/or 14 and the molding compound 100(see length D_(p) in FIG. 4B) for about 10 μm to 100 μm, preferably 50μm to 70 μm.

In one or more embodiments, the enlarged end portions 44 may comprise atleast one metal selected out of copper (Cu), nickel (Ni), palladium (Pd)and gold (Au). Preferably, the enlarged end portions 44 comprise copper(Cu).

In one or more embodiments, a further metallic layer may be providedover the enlarged end portions 44. For instance, the further metalliclayer may comprise tin (Sn) plated over the enlarged end portions 44 atthe pads 12 and/or 14.

One or more embodiments may provide improved reliability (e.g., longerlife on board) over previous solutions, e.g., over solutions involvingwettable flanks.

FIGS. 5A to 5G are exemplary of possible steps of a method ofmanufacturing semiconductor devices according to one or moreembodiments. In FIGS. 5A-5G, manufacturing of a pair of semiconductordevices in exemplified.

As exemplified in FIG. 5A, an otherwise conventional leadframe may beprovided as a first manufacturing step. For each semiconductor device,the leadframe may comprise a die pad 14 and respective leads 12.

As exemplified in FIG. 5B, at least one semiconductor die 50 may bemounted on each die pad 14 of the leadframe. For instance, thesemiconductor dies 50 may be attached on the die pads 14 via die attachmaterial 52, e.g., soft-solder die attach material and/or glue.

As exemplified in FIG. 5C, wire bonding may be carried out to provideelectrical coupling between a semiconductor die 50 and the respectiveleads 12 via bonding wires 54.

As exemplified in FIG. 5D, package molding material 100 may be molded toencapsulate the semiconductor dies 50 and the leadframe, leaving exposedthe electrical pads 12 and the thermal pads 14 at the rear side of thesemiconductor devices.

As exemplified in FIG. 5E, a metallic layer 44 may be provided at thepads 12 and/or 14 after molding of the package material 100, therebyproviding metallic “bumps” (the enlarged end portions) at the packageleads. The enlarged end portions 44 may be grown, for instance, bygalvanic plating. The thickness (t) of the enlarged end portions 44 maybe in the range of 10 μm to 100 μm, preferably 50 μm to 70 μm. Thelateral extension (D_(p)) of the enlarged end portions 44 may be in therange of 10 μm to 100 μm, preferably 50 μm to 70 μm. The enlarged endportions 44 may comprise one or more metals selected out of copper (Cu),nickel (Ni), palladium (Pd) and gold (Au).

As exemplified in FIG. 5F, a further metallic layer 56 may be providedover the metallic layer 44, e.g., by plating. The further metallic layer56 may comprise tin (Sn).

As exemplified in FIG. 5G, the manufacturing method may comprisesingulating the semiconductor devices 10, e.g., by cutting or sawingalong sawing lines, as conventional in the art.

As exemplified herein, a semiconductor device (e.g., 10) may comprise:at least one semiconductor die (e.g., 50) electrically coupled (e.g.,54) to a set of electrically conductive leads; and package moldingmaterial (e.g., 100) molded over the at least one semiconductor die andthe electrically conductive leads, wherein at least a portion of theelectrically conductive leads is exposed at a rear surface (e.g., 10A)of the package molding material to provide electrically conductive pads(e.g., 12, 44).

As exemplified herein, the electrically conductive pads may compriseenlarged end portions (e.g., 44) extending at least partially over thepackage molding material, the enlarged end portions configured forcoupling to a printed circuit board (e.g., 30).

As exemplified herein, the electrically conductive pads may comprisebody portions (e.g., stem portions or web portions 12) embedded in thepackage molding material and the enlarged end portions may protrude fromthe package molding material.

As exemplified herein, the enlarged end portions may extend over thepackage molding material sidewise of said body portions for a length(e.g., D_(p)) of 10 μm to 100 μm, preferably 50 μm to 70 μm.

As exemplified herein, the enlarged end portions may comprise galvanicplating grown material.

As exemplified herein, the enlarged end portions may comprise at leastone metal selected out of copper, nickel, palladium and gold, preferablycopper.

As exemplified herein, a thickness (e.g., t) of the enlarged endportions may be in the range of 10 μm to 100 μm, preferably 50 μm to 70μm.

As exemplified herein, a semiconductor device may comprise a metalliclayer (e.g., 56) plated over the enlarged end portions. The metalliclayer may comprise tin.

As exemplified herein, a semiconductor device may comprise a thermallyconductive pad (e.g., 14). The thermally conductive pad may comprise arespective enlarged end portion extending at least partially over thepackage molding material and configured for coupling to a printedcircuit board.

As exemplified herein, a semiconductor device may comprise a quad-flatno-lead package or a land grid array package.

As exemplified herein, a method may comprise: providing a leadframecomprising at least one die pad and at least one respective set ofelectrically conductive leads; mounting at least one semiconductor dieonto the at least one die pad; electrically coupling the at least onesemiconductor die to electrically conductive leads in the respective atleast one set of electrically conductive leads; molding package moldingmaterial onto the at least one semiconductor die and the leadframe, thepackage molding material exposing at least a portion of the electricallyconductive leads at a rear surface of the package molding material toprovide electrically conductive pads; and providing enlarged endportions of the electrically conductive pads extending at leastpartially over the package molding material, the enlarged end portionsconfigured for coupling to a printed circuit board.

Without prejudice to the underlying principles, the details andembodiments may vary, even significantly, with respect to what has beendescribed by way of example only, without departing from the extent ofprotection.

The claims are an integral part of the technical teaching providedherein in respect of the embodiments.

The extent of protection is defined by the annexed claims.

1. A semiconductor device, comprising: a leadframe including a set ofelectrically conductive leads; a semiconductor die electrically coupledto said set of electrically conductive leads; and package moldingmaterial molded over the semiconductor die and the electricallyconductive leads of the leadframe, wherein at least a portion of theelectrically conductive leads is not covered by the package moldingmaterial; electrically conductive pads at said portion of theelectrically conductive leads which are not covered by the packagemolding material; a plating layer on the electrically conductive padsthat forms first enlarged end portions wherein said plating layerextends at least partially over a rear surface of the package moldingmaterial; wherein the first enlarged end portions are configured forcoupling to a printed circuit board.
 2. The semiconductor device ofclaim 1, wherein the electrically conductive leads comprise bodyportions embedded in the package molding material and said plating layerforming the first enlarged end portions protrudes from the body portionsat the rear surface of the package molding material.
 3. Thesemiconductor device of claim 2, wherein the plating layer forming thefirst enlarged end portions extends over the rear surface of the packagemolding material sidewise of said body portions for a length of 10 μm to100 μm.
 4. The semiconductor device of claim 2, wherein the platinglayer forming the first enlarged end portions extend over the rearsurface of the package molding material sidewise of said body portionsfor a length of 50 μm to 70 μm.
 5. The semiconductor device of claim 1,wherein said plating layer forming the first enlarged end portionscomprises copper.
 6. The semiconductor device of claim 1, wherein saidplating layer forming the first enlarged end portions comprises at leastone metal selected from the group consisting of: nickel, palladium andgold.
 7. The semiconductor device of claim 1, wherein a thickness of theplating layer forming said first enlarged end portions is in a range of10 μm to 100 μm.
 8. The semiconductor device of claim 1, wherein athickness of the plating layer forming said first enlarged end portionsis in a range of 50 μm to 70 μm.
 9. The semiconductor device of claim 1,further comprising a metallic layer plated over the plating layerforming said first enlarged end portions.
 10. The semiconductor deviceof claim 9, wherein the metallic layer comprises tin.
 11. Thesemiconductor device of claim 1, wherein said leadframe furthercomprises a thermally conductor to which the semiconductor die ismounted, wherein at least a portion of the thermally conductor that isnot covered by the package molding material provides a thermallyconductive pad; and wherein said plating layer is also present on thethermally conductive pad to form a second enlarged end portion extendingat least partially over the rear surface of the package moldingmaterial.
 12. The semiconductor device of claim 1, configured as aquad-flat no-lead package.
 13. The semiconductor device of claim 1,configured as a land grid array package.
 14. A semiconductor device,comprising: a semiconductor die mounted to a thermally conductive padand electrically coupled to a set of electrically conductive leads;package molding material molded over the semiconductor die, thethermally conductive pad and the electrically conductive leads, whereinat least a portion of the thermally conductive pad is exposed at a rearsurface of the package molding material; and a plating layer on thethermally conductive pad forming an enlarged portion extending at leastpartially over the rear surface of the package molding material, whereinthe enlarged portion is configured for coupling to a printed circuitboard.
 15. The semiconductor device of claim 14, wherein the thermallyconductive pad comprises a body portion embedded in the package moldingmaterial and the plating layer forming said enlarged end portionprotrudes from the rear surface of the package molding material.
 16. Thesemiconductor device of claim 15, wherein the plating layer forming saidenlarged end portion extends over the rear surface of the packagemolding material sidewise of said body portions for a length of 10 μm to100 μm.
 17. The semiconductor device of claim 15, wherein the platinglayer forming said enlarged end portion extends over the rear surface ofthe package molding material sidewise of said body portions for a lengthof 50 μm to 70 μm.
 18. The semiconductor device of claim 15, wherein theplating layer forming said enlarged end portion comprises at least onemetal selected from the group consisting of: copper, nickel, palladiumand gold.
 19. The semiconductor device of claim 14, wherein a thicknessof plating layer forming said enlarged end portion is in a range of 10μm to 100 μm.
 20. The semiconductor device of claim 14, wherein athickness of the plating layer forming said enlarged end portion is in arange of 50 μm to 70 μm.
 21. The semiconductor device of claim 14,further comprising a metallic layer plated over the plating layerforming said enlarged end portion.
 22. The semiconductor device of claim21, wherein the metallic layer comprises tin.